Module Information
ObjectivesTargeted AudiencePrerequisitesContent SummaryConditionsDurationCertificate
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- Gain a basic working knowledge on SystemVerilog.
- Know how to use the principal aspects of the SystemVerilog language used in verification.
- Be able to build SystemVerilog testbenches using random generation and functional coverage
Design Verification Engineers willing to learn SystemVerilog to develop testbenches or prior to join a UVM training
Experience in using either Verilog or VHDL language for design or for building testbenches (ideally verilog)
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- General programming knowledge: data types, loops, procedural programming such as C, Python, Perl, …
- Basic knowledge of object-oriented programming is a plus but is not strictly required
This module goes through the main SystemVerilog elements used in verification:
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- General Syntax
- Notion of interfaces
- Object Oriented Programming
- Constrained Random Generation
- Functional Coverage
Course openned within 1 to 3 months prior to start
Subject to validation of the prerequisites and objectives survey
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- Learners should have legal and valid accesses to one of the following simulators from their employers:
- SIEMENS Questa
- CADENCE Xcelium
- SYNOPSYS VCS
- English Level B2 minimum
- Learners should have legal and valid accesses to one of the following simulators from their employers:
Online Content Time | 10h |
Est. Indep. Learning Time | 10h |
Workshop time | 7h |
Live Integratin Time | 3h |
Est. Prep. Time | 30min |
Checkpoint Time | 30min |
A certificate of success will be delivered after completion of 60% of the labs and a score of 60% on the final checkpoint
Training Module Content
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Introduction
SystemVerilog
Section Content
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0/13 Steps
TM101_LI02_SLD – Live Integration – SystemVerilog Fundamentals Q&A ( 1h30 )*
Virtual (Required)
SystemVerilog for Verification
Section Content
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0/11 Steps
Section Content
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0/1 Steps
Section Content
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Checkpoint
CPT_CHK: Live Checkpoint
In-Person (Required)