TM101 – SystemVerilog Fundamentals for Verification

Current Status
Not Enrolled
Price
Closed

Module Information

ObjectivesTargeted AudiencePrerequisitesContent SummaryConditionsDurationCertificate

    • Gain a basic working knowledge on SystemVerilog.
    • Know how to use the principal aspects of the SystemVerilog language used in verification.
    • Be able to build SystemVerilog testbenches using random generation and functional coverage

Design Verification Engineers willing to learn SystemVerilog to develop testbenches or prior to join a UVM training

Experience in using either Verilog or VHDL language for design or for building testbenches (ideally verilog)

    • General programming knowledge: data types, loops, procedural programming such as C, Python, Perl, …
    • Basic knowledge of object-oriented programming is a plus but is not strictly required

This module goes through the main SystemVerilog elements used in verification:

    • General Syntax
    • Notion of interfaces
    • Object Oriented Programming
    • Constrained Random Generation
    • Functional Coverage

Course openned within 1 to 3 months prior to start
Subject to validation of the prerequisites and objectives survey

    • Learners should have legal and valid accesses to one of the following simulators from their employers:
      • SIEMENS Questa
      • CADENCE Xcelium
      • SYNOPSYS VCS
    • English Level B2 minimum

Online Content Time 10h
Est. Indep. Learning Time 10h
Workshop time 7h
Live Integratin Time 3h
Est. Prep. Time 30min
Checkpoint Time 30min

A certificate of success will be delivered after completion of 60% of the labs and a score of 60% on the final checkpoint

Training Module Content

Expand All
Section Content
0% Complete 0/1 Steps