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Get Started with this LMS

A propos de cette presentation

Dans cette vidéo, vous apprendrez à utiliser notre système de formation en ligne (Learning Management System ou LMS).

Cette présentation est en anglais, comme l’ensemble de nos formations. Un niveau d’anglais professionnel minimum en lecture et en écoute est donc demandé.

About this presentation

In this video, we present our Learning Management System (LMS) as part of our training process.

You will learn how to use the LMS and navigate through your trainings.

Get Started with the LMS

This presentation is provided for free under our general internal training rules: Internal Regulations / Réglement intérieur (pdf)

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Our Trainings

A propos (FR)

La plupart de nos formations sont disponibles aux formats MILLI (Modular Independent Learning with Live Integration), et donc en mode mixte synchrone/asynchrone supervisé par un formateur.

Voir notre site AEDVICES pour plus d’informations sur le modèle de formation: https://aedvices.com/formations/

Nos formations peuvent être adaptée à vos besoins. Des contenus complémentaires sont aussi disponibles.

Contactez nous via notre formulaire de contact

About (EN)

Most of our trainings are available in the MILLI format (Modular Independent Learning with Live Integration), therefore in mixed asynchronous/synchronous mode with a trainer support.

See our company web site to learn about our training process: https://aedvices.com/en/training/

Additional and taylored trainings may be available upon request.

Contact us via our Training Request form for more information.

TM101 – SystemVerilog Fundamentals for Verification

This module goes through the main SystemVerilog elements used in verification:

    • General Syntax
    • Notion of interfaces
    • Object Oriented Programming
    • Constrained Random Generation
    • Functional Coverage
Enroll Now

TM102 – SystemVerilog for RTL Design

This module goes trough the main SystemVerilog design constructs.

  • Review of the main Verilog syntax (module, reg, always, assign, …)
  • SystemVerilog types (logic, struct, arrays, …)
  • Interfaces
  • Packages
  • Testbenches using SystemVerilog classes, random generation
Enroll Now

TM103: SVA for Designers

    • Introduction to Assertions
    • Design Assertions vs Functional Assertions
    • The different types of SystemVerilog Assertions  
    • The main SystemVerilog assertions operators
    • Simulation vs Formal
    • Using a formal tool to verify simple assertions
Enroll Now

TM202 – UVM Know-How for Verification Engineers

    • UVM main classes
    • Phases
    • The configuration db
    • Objections
    • Agent structure (agent, driver, monitor, sequencer, virtual interface, configuration)
    • Scoreboards

 

Enroll Now

TM250 – Advanced Verification using SystemVerilog and UVM

    • UVM Callback & Factory
    • Advanced Sequences
    • Register Abstraction Layer Modeling
    • Build a Verification IP
    • DPI-C
    • TLM ports
Enroll Now

VS201-CMN – Verification Fundamentals

Common courses for all Verification School (VS) modules:

  • Introduction to Verification
  • Debug Methodology to gain in productivity
  • Verifier’s guide to On-Chip Buses, Interconnects and External I/Os
  • Makefile and Scripting with TCL
Enroll Now
Verification Project Management

VS202-VPM – Verification Project Management

    • Verification as a process
    • The different types of verification strateges and approaches
    • Verification Project Reporting using Metrics and Coverage
    • Build a Verification Plan

 

Enroll Now

VS203-UVMU – Verification Methodology using UVM

  • SystemVerilog Fundamentals
  • SystemVerilog for Coverage Driven Verification
  • UVM Fundamentals
  • UVM Must Know
Enroll Now

VS204-UVMA – Architecting Advanced UVM Environments

  • Build a Verification IP
  • UVM Register Abstraction Layer
  • UVM Advanced Sequences
  • UVM details on the factory, callbacks, TLM ports
  • Using the DPI in a UVM environment
Enroll Now

VS206 – Soc Level Verification Methodologies and Techniques

  • SoC Level Verification Challenges
  • Bare Metal Boot Software Driven Verification at SoC Level
  • Directed SoC Level Verification
  • Automated SoC Level Verification & Vertical Reuse
Enroll Now
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