TM102 – SystemVerilog for RTL Design

Current Status
Not Enrolled

Module Information

ObjectivesTargeted AudiencePrerequisitesContent SummaryConditionsDurationCertificate

Be able to use SystemVerilog design constructs

    • to simplify my RTL designs
    • to be more productive
    • to understand what I’m doing

Know the principal SystemVerilog constructs used to build testbenches

Designers with Verilog or VHDL Background willing to use SystemVerilog to develop their designs

  • Have a VHDL design experience of over 1 year and have followed a training “Verilog for VHDL Designers” or equivalent
  • Have a Verilog design experience of over 1 year

This module goes trough the main SystemVerilog design constructs.

  • Review of the main Verilog syntax (module, reg, always, assign, …)
  • SystemVerilog types (logic, struct, arrays, …)
  • Interfaces
  • Packages
  • Testbenches using SystemVerilog classes, random generation

  • Course openned within 1 to 3 months prior to start
  • Subject to validation of the prerequisites and objectives survey
  • Learners should have legal and valid accesses to one of the following simulators from their employers:
    • SIEMENS Questa
    • CADENCE Xcelium
  • English Level B2 minimum

Online Content Time 10h
Est. Indep. Learning Time 10h
Workshop time 7h
Live Integratin Time 3h
Est. Prep. Time 30min
Checkpoint Time 30min

A certificate of success will be delivered after completion of 60% of the labs and a score of 60% on the final checkpoint