VS204-UVMA – Architecting Advanced UVM Environments

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Not Enrolled
Price
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Module Information

ObjectivesTargeted AudiencePrerequisitesContent SummaryConditionsDurationCertificate

Be able to architect a UVM Verification Environment including:

    • Be able to implement a Verification IP
    • Be able to implement a register abstraction layer and prediction
    • Be able to write complex random test sequences
    • Be able to use the DPI-C efficiently to connect to a reference model or to control a sequence

Engineers with a first UVM experience willing to leverage their skills to resolve complex problems

Prior to this course, students should have experienced using UVM on a first project.
In particular, 

    • they have experiences in writing test sequences
    • they are able to instantiate and use a Verification IP or a UVM agent
    • they are able to implement a scoreboard

Notions of C programming is requested for the DPI part.

Materials and videos are in English, a level B2 in English is required.

  • Build a Verification IP
  • UVM Register Abstraction Layer
  • UVM Advanced Sequences
  • UVM details on the factory, callbacks, TLM ports
  • Using the DPI in a UVM environment

  • Course openned within 1 to 3 months prior to start
  • Subject to validation of the prerequisites and objectives survey
  • Learners should have legal and valid accesses to one of the following simulators from their employers:
    • SIEMENS Questa
    • CADENCE Xcelium
    • SYNOPSYS VCS
  • English Level B2 minimum

Online Content Time 12h
Est. Indep. Learning Time 12h
Workshop time 7h
Live Integratin Time 4.5h
Est. Prep. Time 30min
Checkpoint Time 30min

A certificate of success will be delivered after completion of 60% of the labs and a score of 60% on the final checkpoint

Training Module Content

Expand All
PART 1 - VIP
PART 2 - RAL
PART 3 - SEQUENCES, DPI & ASSERTION
CLOSING