VS204-UVMA – Architecting Advanced UVM Environments

Be able to architect a UVM Verification Environment from scratch including:

• Be able to implement a Verification IP
• Be able to implement a register abstraction layer and prediction
• Be able to write complex random test sequences
• Be able to use the DPI-C efficiently to connect to a reference model or to control a sequence

Engineers with a first UVM experience willing to leverage their skills to resolve complex problems

Prior to this course, students should have experienced using UVM on a first project.
In particular, 

• they have experiences in writing test sequences
• they are able to instantiate and use a Verification IP or a UVM agent
• they are able to implement a scoreboard

Notions of C programming is requested for the DPI part.

Materials and videos are in English, a level B2 in English is required.

Live Sessions will be in English or French depending on your request.
Contents, Videos and Materials are provided in English.

An English level C1 is recommended ( minimum B2 )

The course is built around the following key aspects:

• Build a Verification IP
• Mastering the UVM Register Abstraction Layer
• Develop any types of complex sequences using UVM advanced sequence features
• UVM details on the factory, callbacks, TLM ports
• Using the DPI in a UVM environment

• Course openned within 1 to 3 months prior to start
• Subject to validation of the prerequisites and objectives survey
• Learners should have legal and valid accesses to one of the following simulators from their employers:
  • SIEMENS Questa
  • CADENCE Xcelium
  • SYNOPSYS VCS
• English Level B2 minimum

A certificate of success will be delivered after completion of 60% of the labs and a score of 60% on the final checkpoint