TM101 – SystemVerilog for Verification Engineers

Design Verification Engineers willing to learn SystemVerilog to develop testbenches or prior to join a UVM training

Experience in using either Verilog or VHDL language for design or for building testbenches (ideally verilog)

• • General programming knowledge: data types, loops, procedural programming such as C, Python, Perl, …
  • Basic knowledge of object-oriented programming is a plus but is not strictly required

This module goes through the main SystemVerilog elements used in verification:

• • General Syntax
  • Notion of interfaces
  • Object Oriented Programming
  • Constrained Random Generation
  • Functional Coverage

Course openned within 1 to 3 months prior to start
Subject to validation of the prerequisites and objectives survey

• • Learners should have legal and valid accesses to one of the following simulators from their employers:
    • SIEMENS Questa
    • CADENCE Xcelium
    • SYNOPSYS VCS
  • English Level B2 minimum

A certificate of success will be delivered after completion of 60% of the labs and a score of 60% on the final checkpoint