TM103: SVA for Designers

Be able to use SVA assertions as part of the RTL design process

• • Be able to check design intent using SVA
  • Know the different types of assertions
  • Be able to use immediate (boolean) assertions within the code
  • Be able to use concurrent assertions to check time consuming events

Design Engineers willing to add assertions to improve their productivity

• • Designers with RTL experience in Verilog
    • Be able to write Verilog RTL designs
    • Basic notions of C Programming
  • English B2

Live Sessions will be in English or French depending on your request.
Contents, Videos and Materials are provided in English.

An English level C1 is recommended ( minimum B2 )

• • Introduction to Assertions
  • Design Assertions vs Functional Assertions
  • The different types of SystemVerilog Assertions  
  • The main SystemVerilog assertions operators
  • Simulation vs Formal
  • Using a formal tool to verify simple assertions

Course openned within 1 to 3 months to organisations, starting from a group of 3 minium.

Subject to validation of the prerequisites and objectives.

Learners should have legal and valid accesses to one of the following EDA tools from their employers:

• • SIEMENS Questa
  • CADENCE Xcelium
  • (Synopsys VCS support planned in Q3-2024 – contact us if more urgent)

and to the formal verification tool:

• • CADENCE Jasper
  • SIEMENS Questa Formal (planned in Q4-2024 – contact us if more urgent)

A certificate of success will be delivered after completion of 60% of the labs and a score of 60% on the final checkpoint