TM200 – UVM Fundamentals for Coverage Driven Verification

• • Be able to work on UVM projects
    • Be able to instantiate and use a UVM Verification IP
    • Be able to write UVM sequences
    • Be able to implement a scoreboard
  • Be able to develop simple UVM agent

Verification Engineers starting with UVM

Having knowledge in SystemVerilog for verification (classes, interfaces, random generation, covergroups)

Courses are either in French or in English and training materials is provided in English. 

Live Sessions will be in English or French depending on your request.
Contents, Videos and Materials are provided in English.

An English level C1 is recommended ( minimum B2 )

• • UVM main classes
  • Phases
  • The configuration db
  • Objections
  • Agent structure (agent, driver, monitor, sequencer, virtual interface, configuration)
  • Scoreboards

• • Course openned within 1 to 3 months prior to start
  • Subject to validation of the prerequisites and objectives survey
  • Learners should have legal and valid accesses to one of the following simulators from their employers:
    • SIEMENS Questa
    • CADENCE Xcelium
    • SYNOPSYS VCS
  • English Level B2 minimum

A certificate of success will be delivered after completion of 60% of the labs and a score of 60% on the final checkpoint