TM202 – UVM Know-How for Verification Engineers

• • Be able to work on UVM projects
    • Be able to instantiates and use a UVM Verification IP
    • Be able to write UVM sequences
    • Be able to implement a scoreboard
  • Be able to write simple UVM agent

Having knowledge in SystemVerilog for verification (classes, interfaces, random generation, covergroups)

• • UVM main classes
  • Phases
  • The configuration db
  • Objections
  • Agent structure (agent, driver, monitor, sequencer, virtual interface, configuration)
  • Scoreboards

• • Course openned within 1 to 3 months prior to start
  • Subject to validation of the prerequisites and objectives survey
  • Learners should have legal and valid accesses to one of the following simulators from their employers:
    • SIEMENS Questa
    • CADENCE Xcelium
    • SYNOPSYS VCS
  • English Level B2 minimum

A certificate of success will be delivered after completion of 60% of the labs and a score of 60% on the final checkpoint