TM250 – Advanced Verification using SystemVerilog and UVM

Current Status
Not Enrolled

Module Information

ObjectivesTargeted AudiencePrerequisitesContent SummaryConditionsDurationCertificate

    • Be able to develop advanced sequences
      • using the sequence arbitration scheme
      • using random selections
      • building sequence libraries
      • build reactive sequences
    • Be able to develop a complete Verification IP from scratch
    • Be able to implement a Register Abstraction Layer prediction and connect it to a scoreboard
    • Be able to interface UVM with external C models

Verification Engineers with a first experience in UVM willing to solve complex verification problems

Have a confirmed experience in using UVM

    • UVM Callback & Factory
    • Advanced Sequences
    • Register Abstraction Layer Modeling
    • Build a Verification IP
    • DPI-C
    • TLM ports

    • Course openned within 1 to 3 months prior to start
    • Subject to validation of the prerequisites and objectives survey
    • Learners should have legal and valid accesses to one of the following simulators from their employers:
      • SIEMENS Questa
      • CADENCE Xcelium
    • English Level B2 minimum

Online Content Time 14h
Est. Indep. Learning Time 14h
Workshop time 7h
Live Integratin Time 3h
Est. Prep. Time 30min
Checkpoint Time 30min

A certificate of success will be delivered after completion of 60% of the labs and a score of 60% on the final checkpoint

Training Module Content

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