TM300 – Advanced Verification Techniques using SystemVerilog and UVM

• • Be able to develop advanced sequences
    • using the sequence arbitration scheme
    • using random selections
    • building sequence libraries
    • build reactive sequences
  • Be able to develop a complete Verification IP from scratch
  • Be able to implement a Register Abstraction Layer prediction and connect it to a scoreboard
  • Be able to interface UVM with external C models

Verification Engineers with a first experience in UVM willing to solve complex verification problems

Have a confirmed experience in using UVM

• • UVM Callback & Factory
  • Advanced Sequences
  • Register Abstraction Layer Modeling
  • Build a Verification IP
  • DPI-C
  • TLM ports

• • Course openned within 1 to 3 months prior to start
  • Subject to validation of the prerequisites and objectives survey
  • Learners should have legal and valid accesses to one of the following simulators from their employers:
    • SIEMENS Questa
    • CADENCE Xcelium
    • SYNOPSYS VCS
  • English Level B2 minimum

A certificate of success will be delivered after completion of 60% of the labs and a score of 60% on the final checkpoint