TM500-SV: SystemVerilog for Verification

Following this course, learners will be able to 

• • Use SystemVerilog in testbenches.
  • Use the principal aspects of the SystemVerilog language used in verification (classes, constraints, coverage).
  • Build SystemVerilog testbenches using random generation and functional coverage

This module goes through the main SystemVerilog elements used in verification:

• • General Syntax
  • Notion of interfaces
  • Object Oriented Programming
  • Constrained Random Generation
  • Functional Coverage

Experience in using either Verilog or VHDL language for design or for building testbenches (ideally verilog)

• General programming knowledge: data types, loops, procedural programming such as C, Python, Perl, …
• Basic knowledge of object-oriented programming is a plus but is not strictly required

• Course openned within 1 to 3 months prior to start
• Subject to validation of the prerequisites and objectives survey
• Learners should have legal and valid accesses to one of the following simulators from their employers:
  • SIEMENS Questa
  • CADENCE Xcelium
  • SYNOPSYS VCS
• English Level B2 minimum

When given in the MILLI format, the training will allow students to meet with trainers on key topics for each section:

Live Integration	TM500_LI00	Kick-Off Live Integration **	00h45
Live Integration	TM500_LI01	Live Integration – SystemVerilog Fundamentals ( preparation ~5 minutes / meeting 1h30 ) ***	01h30
Live Integration	TM500_LI02	Live Integration – SystemVerilog Verification Constructs	01h30
Workshop	TM500_WS01	Workshop – Build a Coverage Driven SystemVerilog Testbench 1/2	03h30
Workshop	TM500_WS02	Workshop – Build a Coverage Driven SystemVerilog Testbench 2/2	03h30
Checkpoint	CPT_CHK	Live Checkpoint	00h30