VS203-UVMU – Verification Methodology using UVM

Current Status
Not Enrolled

Module Information

ObjectivesTargeted AudiencePrerequisitesContent SummaryConditionsDurationCertificate

The objective of this module is to be able to use SystemVerilog and UVM to verify an IP using existing UVM Verification Components ( VIP / uVC ), including:

    • Be able to instantiate Verification IPs and create a UVM testbench.
    • Be able to implement coverage metrics in line with a verification plan to report verification progress
    • Be able to implement checkers using scoreboards and simple assertions

Digital Microelectronics Engineers starting with SystemVerilog and UVM

  • General hardware design and architecture knowledge
  • Basic scripting know-how
  • Basic programming know-how (C , Python , … )
  • Knowledge of a Hardware Description Language such as VHDL or Verilog
  • Simulation know-how

  • SystemVerilog Fundamentals
  • SystemVerilog for Coverage Driven Verification
  • UVM Fundamentals
  • UVM Must Know

  • Course openned within 1 to 3 months prior to start
  • Subject to validation of the prerequisites and objectives survey
  • Learners should have legal and valid accesses to one of the following simulators from their employers:
    • SIEMENS Questa
    • CADENCE Xcelium
  • English Level B2 minimum

Online Content Time 14h
Est. Indep. Learning Time 14h
Workshop time 7h
Live Integratin Time 4.5h
Est. Prep. Time 45min
Checkpoint Time 30min

A certificate of success will be delivered after completion of 60% of the labs and a score of 60% on the final checkpoint

Training Module Content

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