VS205-FV – Formal Verification

Develop a formal verification approach and know-how to prove complex assertions using formal tools:

• Be able to develop complex assertions in SVA
• Be able to prove complex assertions using formal tools

For verification engineers involved or planning to be involved in Formal Verification

• SystemVerilog Assertions
• Assertions Based Verification
• Property Checking

• Course openned within 1 to 3 months prior to start
• Subject to validation of the prerequisites and objectives survey
• Learners should have legal and valid accesses to one of the following simulators from their employers:
  • SIEMENS Questa Formal or OneSpin
  • CADENCE JasperGold
  • SYNOPSYS VCS Formal
• English Level B2 minimum

A certificate of success will be delivered after completion of 60% of the labs and a score of 60% on the final checkpoint