VS205-FV – Formal Verification

Current Status
Not Enrolled

Module Information

ObjectivesTargeted AudiencePrerequisitesContent SummaryConditionsDurationCertificate

Develop a formal verification approach and know-how to prove complex assertions using formal tools:

  • Be able to develop complex assertions in SVA
  • Be able to prove complex assertions using formal tools


Verification Engineers moving to formal verification to verify critical functionalities

Engineers with

  • A first experience in Verification activity
  • RTL Simulation know-how
  • Be able to develop testbenches Verilog or SystemVerilog
  • English B2

  • SystemVerilog Assertions
  • Assertions Based Verification
  • Property Checking

  • Course openned within 1 to 3 months prior to start
  • Subject to validation of the prerequisites and objectives survey
  • Learners should have legal and valid accesses to one of the following simulators from their employers:
    • SIEMENS Questa Formal or OneSpin
    • CADENCE JasperGold
    • SYNOPSYS VCS Formal
  • English Level B2 minimum

Online Content Time 7h
Est. Indep. Learning Time 7h
Workshop time 10.5h
Live Integratin Time 3h
Est. Prep. Time 30min
Checkpoint Time 30min

A certificate of success will be delivered after completion of 60% of the labs and a score of 60% on the final checkpoint

Training Module Content

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