VS205-FV – Formal Verification

Develop a formal verification approach and practical know-how to prove complex assertions using formal tools:

• Be able to develop complex assertions in SVA
• Be able to prove complex assertions using a formal tool

Verification Engineers moving to formal verification to verify critical functionalities

This training is open to engineers with a minimum prerequisites in verification engineering

• A first experience in Verification activity (simulation or formal)
• RTL Simulation know-how
• Be able to develop testbenches Verilog or SystemVerilog
• English B2

This course is built around the following key aspects:

• SystemVerilog Assertions
• Assertions Based Verification
• Formal Property Checking
• Functional Verification using formal tools
• Using coverage with formal tools

• Course openned within 1 to 3 months prior to start
• Subject to validation of the prerequisites and objectives survey
• Learners should have legal and valid accesses to one of the following simulators from their employers:
  • SIEMENS Questa Formal or OneSpin
  • CADENCE JasperGold
  • SYNOPSYS VCS Formal
• English Level B2 minimum

A certificate of success will be delivered after completion of 60% of the labs and a score of 60% on the final checkpoint