VS206 – Soc Level Verification Methodologies and Techniques

Current Status
Not Enrolled
Price
Closed

Module Information

ObjectivesTargeted AudiencePrerequisitesContent SummaryConditionsDurationCertificate

Be able to implement SoC Level Verification

    • Be able to develop SoC Level test following a verification plan
    • Be able to develop software driven tests at SoC Level
    • Be able to implement test automation at SoC Level
    • Understand how and why to use UVM at SoC Level
    • Be able to use coverage metrics and assertions at SoC Level

For IP Verification Engineers willing to move to the SoC Level Verification level
For Verification Engineers starting a project at SoC Level

For engineers involved in SoC Level Verification

    • General hardware design and architecture knowledge
    • General knowledge on SoC architecture
    • English B2

  • SoC Level Verification Challenges
  • Bare Metal Boot Software Driven Verification at SoC Level
  • Directed SoC Level Verification
  • Automated SoC Level Verification & Vertical Reuse

  • Course openned within 2 to 3 months prior to start
  • Subject to validation of the prerequisites and objectives survey
  • Learners should have legal and valid accesses to one of the following simulators from their employers:
    • SIEMENS Questa
    • CADENCE Xcelium
    • SYNOPSYS VCS
  • English Level B2 minimum

Online Content Time 10h
Est. Indep. Learning Time 10h
Workshop time 7h
Live Integratin Time 3h
Est. Prep. Time 30min
Checkpoint Time 30min

A certificate of success will be delivered after completion of 60% of the labs and a score of 60% on the final checkpoint