VS206 – Soc Level Verification Methodologies and Techniques

SOC_0021_LAB:
Pulp SoC Architecture Discovery ( ~ 1h )

SOC_0022_LAB:
SoC Environment Discovery ( ~1h30 )

SOC_0031_LAB:
Architecting a SoC Level Testbench ( ~1h30 )

SOC_0100_LAB:
Build a SoC Level Verification Plan ! TO BE DONE AT LEAST 3 DAYS BEFORE THE LIVE INTEGRATION ! ( ~1h30 )

SOC_1010_LAB:
Setting up the tool chain ( ~1h00 )

SOC_1020_LAB:
Setting up the scatter/linker file and the memory loader ( ~1h00 )

SOC_1030_LAB: Booting a SoC / Crash Test Boot ( ~1h30 )

SOC_1040_LAB:
Writting a register test ( ~0h45 )

SOC_1050_LAB:
Writting an interrupt handler ( ~0h45 )

SOC_2011_LAB:
Connectivity Tests using assertions and formal ( ~0h45 )

SOC_2021_LAB:
DMA Integration tests ( ~1h00 )

SOC_2031_LAB:
Memory Integration tests ( ~0h45 )

SOC_2041_LAB:
Checking UART using loopback testbench ( ~0h45 )

SOC_2042_LAB:
UART Integration Test ( ~0h45 )

SOC_2051_LAB:
Controlloing external testbench through virtual registers ( ~0h00 )

10:
Checking Timers and Interrupts ( ~0h00 )

SOC_3010_LAB: Automating Register Test ( ~0h00 )

SOC_3030_LAB: Headless SoC controlled by UVM Sequences ( ~0h00 )

SOC_3300_LAB: Get started with PSS ( ~0h00 )