A propos (FR)

La plupart de nos formations sont disponibles aux formats MILLI (Modular Independent Learning with Live Integration), et donc en mode mixte synchrone/asynchrone supervisé par un formateur.

Voir notre site AEDVICES pour plus d’informations sur le modèle de formation: https://aedvices.com/formations/

Nos formations peuvent être adaptée à vos besoins. Des contenus complémentaires sont aussi disponibles.

Contactez nous via notre formulaire de contact

About (EN)

Most of our trainings are available in the MILLI format (Modular Independent Learning with Live Integration), therefore in mixed asynchronous/synchronous mode with a trainer support.

See our company web site to learn about our training process: https://aedvices.com/en/training/

Additional and taylored trainings may be available upon request.

Contact us via our Training Request form for more information.

Architecting Advanced UVM Environments (TM502-UVMA)

The course is built around the following key aspects:

  • Build a Verification IP
  • Mastering the UVM Register Abstraction Layer
  • Develop any types of complex sequences using UVM advanced sequence features
  • UVM details on the factory, callbacks, TLM ports
  • Using the DPI in a UVM environment
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SystemVerilog for Verification [TM500-SV]

This module goes through the main SystemVerilog elements used in verification:

    • General Syntax
    • Notion of interfaces
    • Object Oriented Programming
    • Constrained Random Generation
    • Functional Coverage
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TM100 – SystemVerilog for Verification Engineers

This module goes through the main SystemVerilog elements used in verification:

    • General Syntax
    • Notion of interfaces
    • Object Oriented Programming
    • Constrained Random Generation
    • Functional Coverage
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TM102 – SystemVerilog for RTL Design

This module goes trough the main SystemVerilog design constructs.

  • Review of the main Verilog syntax (module, reg, always, assign, …)
  • SystemVerilog types (logic, struct, arrays, …)
  • Interfaces
  • Packages
  • Testbenches using SystemVerilog classes, random generation
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TM103: SVA for Designers

    • Introduction to Assertions
    • Design Assertions vs Functional Assertions
    • The different types of SystemVerilog Assertions  
    • The main SystemVerilog assertions operators
    • Simulation vs Formal
    • Using a formal tool to verify simple assertions
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TM200 – UVM Fundamentals for Coverage Driven Verification

    • UVM main classes
    • Phases
    • The configuration db
    • Objections
    • Agent structure (agent, driver, monitor, sequencer, virtual interface, configuration)
    • Scoreboards

 

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TM300 – Advanced Verification Techniques using SystemVerilog and UVM

    • UVM Callback & Factory
    • Advanced Sequences
    • Register Abstraction Layer Modeling
    • Build a Verification IP
    • DPI-C
    • TLM ports
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TM600 – Verification Plan – From Specification to Project Metrics and Tracking

  • The Process of the Verification Activity as part of the overall project
  • The Different Types of Verification Strategies and Approaches, with their pros and cons
  • The Verification Project Reporting using Metrics and Coverage as the main KPIs
  • How to Build a Verification Plan

 

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VS202-VPM – Verification Project Management

  • The Process of the Verification Activity as part of the overall project
  • The Different Types of Verification Strategies and Approaches, with their pros and cons
  • The Verification Project Reporting using Metrics and Coverage as the main KPIs
  • How to Build a Verification Plan

 

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VS205-FV – Formal Verification

This course is built around the following key aspects:

  • SystemVerilog Assertions
  • Assertions Based Verification
  • Formal Property Checking
  • Functional Verification using formal tools
  • Using coverage with formal tools
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VS206 – Soc Level Verification Methodologies and Techniques

This training is articulated around the following key aspects:

  • From SoC Level Verification Challenges to a comprehensive Methodology
  • Bare Metal & Software Driven Verification at SoC Level
  • Directed SoC Level Verification
  • Leveraging the SoC Level Verification with Automation & Vertical Reuse
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