This module goes through the main SystemVerilog elements used in verification:
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- General Syntax
- Notion of interfaces
- Object Oriented Programming
- Constrained Random Generation
- Functional Coverage
TM102 – SystemVerilog for RTL Design
This module goes trough the main SystemVerilog design constructs.
- Review of the main Verilog syntax (module, reg, always, assign, …)
- SystemVerilog types (logic, struct, arrays, …)
- Interfaces
- Packages
- Testbenches using SystemVerilog classes, random generation
TM103: SVA for Designers
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- Introduction to Assertions
- Design Assertions vs Functional Assertions
- The different types of SystemVerilog Assertions
- The main SystemVerilog assertions operators
- Simulation vs Formal
- Using a formal tool to verify simple assertions
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TM202 – UVM Fundamentals for Coverage Driven Verification
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- UVM main classes
- Phases
- The configuration db
- Objections
- Agent structure (agent, driver, monitor, sequencer, virtual interface, configuration)
- Scoreboards
TM250 – Advanced Verification using SystemVerilog and UVM
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- UVM Callback & Factory
- Advanced Sequences
- Register Abstraction Layer Modeling
- Build a Verification IP
- DPI-C
- TLM ports
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VS200-eVTB – Essentials Verification Tool Box
Common courses for all Verification School (VS) modules:
- Introduction to Verification
- Debug Methodology to gain in productivity
- Verifier’s guide to On-Chip Buses, Interconnects and External I/Os
- Makefile and Scripting with TCL
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VS201-CMN – Common Verification Essential Topics
Common courses for all Verification School (VS) modules:
- Introduction to Verification
- Debug Methodology to gain in productivity
- Verifier’s guide to On-Chip Buses, Interconnects and External I/Os
- Makefile and Scripting with TCL
VS202-VPM – Verification Project Management (VPlan)
- The Process of the Verification Activity as part of the overall project
- The Different Types of Verification Strategies and Approaches, with their pros and cons
- The Verification Project Reporting using Metrics and Coverage as the main KPIs
- How to Build a Verification Plan
VS203-UVMU – Verification Methodology using UVM
In this course, students will learn how the fundamentals of SystemVerilog and UVM:
- SystemVerilog Language Fundamentals
- SystemVerilog for Coverage Driven Verification
- UVM Fundamentals
- UVM Must Know
VS204-UVMA – Architecting Advanced UVM Environments
The course is built around the following key aspects:
- Build a Verification IP
- Mastering the UVM Register Abstraction Layer
- Develop any types of complex sequences using UVM advanced sequence features
- UVM details on the factory, callbacks, TLM ports
- Using the DPI in a UVM environment
VS205-FV – Formal Verification
This course is built around the following key aspects:
- SystemVerilog Assertions
- Assertions Based Verification
- Formal Property Checking
- Functional Verification using formal tools
- Using coverage with formal tools
VS206 – Soc Level Verification Methodologies and Techniques
This training is articulated around the following key aspects:
- From SoC Level Verification Challenges to a comprehensive Methodology
- Bare Metal & Software Driven Verification at SoC Level
- Directed SoC Level Verification
- Leveraging the SoC Level Verification with Automation & Vertical Reuse
